The present invention relates to an information processing apparatus for a virtual storage control system which has a buffer memory.
A conventional information processing apparatus of this type has a configuration as shown in FIG. 1. Referring to FIG. 1, when a main memory 2 (to be referred to as an MM 2 for brevity hereinafter) is accessed from a central processing unit 1 (to be referred to as a CPU 1 for brevity hereinafter), a virtual address produced on an address bus 3 by the CPU 1 is converted into a real address by an address conversion section 4. The real address is transferred to a main memory controller 6 (to be referred to as an M-CNT 6 for brevity hereinafter) and to a buffer storage 7 through an address bus 5. On the other hand, when the MM 2 is accessed from a channel 8 (or a DMA unit), the virtual address generated by the channel 8 is converted into a real address by an address conversion section 8a within the channel 8. When the number of channel 8 is plural, each channel is provided with the address conversion section 8a. The real address is then transferred through a DMA bus 9 to a DMA controller 10 (to be referred to as a DMA-CNT 10 for brevity hereinafter) for controlling the DMA bus 9. The real address on the DMA bus 9 is transferred to the M-CNT 6 and to the buffer storage 7 under the control of the DMA-CNT 10. The buffer storage 7 comprises a high-speed memory element and is incorporated to achieve high-speed processing (memory access) of the information processing apparatus and stores a copy of part of the contents stored in the MM 2. The buffer storage 7 is accessed by the real address produced from the address conversion section 4 or from the DMA-CNT 10. If the buffer storage 7 is accessed for. memory read and the desired data is stored, the corresponding data is read out on a data bus 11 or on a DMA bus 9. Referring to FIG. 1, reference numeral 12 denotes a memory bus.
In the conventional information processing apparatus of the configuration as described above, the buffer storage 7 must be accessed using the real address which is obtained by address conversion by the address conversion section 4. This results in a long memory access time.
In an information processing apparatus which adopts a multi-virtual storage control technique, the address conversion buffer must be rendered ineffective every time the virtual space is switched. This also applies to the buffer storage. The conventional information processing apparatus requires hardware for this purpose. Moreover, since the address conversion buffer is rendered ineffective, the hit rate in accessing the address conversion buffer is lowered, and the processing speed is decreased.